The present invention is related to capacitor structures in integrated circuits and, in particular, to metal-insulator-metal capacitor structures in multilayer metal integrated circuits.
Current semiconductor processing technologies have enabled the reduction of sizes of transistors to critical dimensions below 0.25 xcexcm. Critical dimensions are now approaching 0.18 xcexcm and even more aggressive technologies are considering critical dimensions of 0.13 xcexcm. The operating frequencies of the resulting integrated circuits have risen to such an extent that MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated circuits are being used for RF (Radio Frequency) applications. Such applications typically have analog and RF circuits which require passive elements, such as capacitors. In conventional MOS processes, including CMOS (Complementary Metal-Oxide-Semiconductor, the particular MOSFET technology of choice today), various capacitor structures, such as junction capacitors or gate capacitors, are available. However, these capacitor structures are voltage-dependent and do not meet the performance of a fixed capacitor, which is typically required in analog and RF circuits.
To satisfy this requirement, recent CMOS processes have provided MIM (metal-insulator-metal) capacitor structures which are implemented in the interconnect metallization layers of the integrated circuit. These multiple metallization layers are formed over the semiconductor substrate in which the source and drain regions of the transistors are defined to interconnect various elements of the integrated circuit. A single masking step can be added in the manufacturing process steps used to create conventional metal layers in the integrated circuit to create the capacitors. However, this results in very low density capacitors, i.e., capacitors with relatively low capacitance per unit area. Since the total area of a MIM capacitor can be a significant portion (15%-30%) of the total substrate area of an integrated RF/Analog/Baseband integrated circuit and can be an even larger portion in a CMOS implementation of the radio section only of the integrated circuit, it is necessary to achieve as high an area density of the capacitance as possible for cost minimization.
On the other hand, the present invention provides for MIM capacitor which has a greatly increased capacitor density. Furthermore, the present invention is readily compatible with current semiconductor processing technologies so that CMOS technologies can easily adopt the present invention.
The present invention provides for a high density capacitor structure between adjacent stacked metal layers in an integrated circuit. The metal layers are delineated as interconnections for the integrated circuit. The capacitor structure has a portion of a first selected one of the stacked metal layers and a portion of a second selected one of the stacked metal layers. The second selected stacked metal layer portion is located above and adjacent the first selected stacked metal layer portion. The capacitor structure also has a first capacitor dielectric layer over the first selected stacked metal layer portion; a first capacitor metal plate layer over the first capacitor dielectric layer; a second capacitor dielectric layer under the second selected stacked metal layer portion; a second capacitor metal plate layer under the second capacitor dielectric layer and over and removed from the first capacitor metal plate layer; and a metal capacitor via layer between and connecting said the capacitor metal plate layer and the second capacitor metal plate layer, and a first via connecting the first selected stacked metal layer portion and the second selected stacked metal layer portion. The metal capacitor via layer forms a first terminal of the capacitor structure; and the first via forms a second terminal of the capacitor structure.
The present invention also provides for a method of manufacturing a high density capacitor structure between first and second metallic interconnections of an integrated circuit. The first and second metallic interconnections are separated by an insulating intermetallic oxide layer and the method has the steps of disposing a first metal-dielectric-metal layer capacitor over and with a portion of the first metallic interconnection portion; disposing a second metal-dielectric-metal layer capacitor under and with a portion of the second metallic interconnection; disposing a first metal via through the insulating intermetallic oxide layer to connect the first metal-dielectric-metal layer capacitor and said second metal-dielectric-metal layer capacitor; and disposing a second metal via through the insulating intermetallic oxide layer to connect the first metallic interconnection portion and said second metallic interconnection portion. The first metal via layer forms a first terminal of the capacitor structure and the second metal via form a second terminal of the capacitor structure.